Double-patterning is currently the subject of considerable research. Generally speaking, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense circuit pattern into two separate, less-dense patterns. The simplified patterns are then printed separately on a target wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense patterns). Further, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either the two masks. This technique effectively lowers the complexity of the lithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be possible.
While it may be easy to determine how to separate a line: space pattern into two separate masks, it can be quite difficult to determine how to separate complex logic designs into separate masks. Current method for performing the separation process is typically complex, can fail to resolve conflicts and may require operation intervention.
Accordingly, it is an object of the present invention to provide a method and apparatus for automatically splitting complex circuit patterns into two or more less complex masks in an efficient and effective manner.